The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a STI structure and fabrication process thereof.
With progress in the art of device miniaturization, it is now possible to fabricate ultrafine/ultra high-speed semiconductor devices having a gate length of less than 100 nm. In such ultrafine/ultra high-speed semiconductor devices, an STI (shallow trench isolation) structure is used commonly as a device isolation structure.
With such ultrafine/ultrahigh speed transistors, it should be noted that the area of the channel region right underneath the gate electrode is far smaller as compared with the case of conventional semiconductor devices, and thus, mobility of electrons or holes traveling through the channel region is influenced heavily by the stress applied to the channel region. Thus, various attempts have been made so far for improving the operational speed of the semiconductor device by optimizing the stress applied to the channel region thereof.